This is a simplified configuration of an EPYC Rome node with two sockets. Each socket contains eight Core Complex Dies (CCDs, each enclosed in a green box) and one I/O die (IOD, enclosed in a yellow box). The infinity sign (♾) represents the Infinity Fabric. Each CCD contains two Core Complexes (CCXs). Each CCX has 4 cores and 16 MB of L3 cache. Thus, there are 64 cores per socket and 128 cores per node.

The Rome processor hierarchy is as follows:

  • Core: A CPU core has private L1I, L1D, and L2 caches, which are shared by two hyperthreads on the core.
  • CCX: A core complex includes four cores and a common L3 cache of 16 MB. Different CCXs do not share L3.
  • CCD: A core complex die includes two CCXs and an Infinity Link to the I/O die (IOD). The CCDs connect to memory, I/O, and each other through the IOD.
  • Socket: A socket includes eight CCDs (total of 64 cores), a common centralized I/O die (includes eight unified memory controllers and eight IO x16 PCIe 4.0 lanes—total of 128 lanes), and a link to the network interface controller (NIC).
  • Node: A node includes two sockets and a network interface controller (NIC).

参考资料:

  1. AMD Rome Processors