本文将mark下DRAM components相关notes。


In modern cloud servers, a CPU(socket) has several memory controllers. Each controller communicates with DIMMs through high-speed memory channels. Usually, a memory channel is shared by several DIMM slots. A DIMM has several ranks, and each is composed of sevaral DRAM chips. For typical DDR4 DIMMs, a rank is composed of 16 chips for data bits and 2 additional chips for ECC bits. A chip consists of multiple banks, which enables the access parallesim. A DRAM bank is structured as a two-dimensional cell array indexed by rows and columns. At the micro-level, a cell can store multiple bits of data, and the number of data bits stored in a cell is called the data width of a chip, which is usually denoted as x4, x8 or x16,etc.

  • socket
  • memory controller
  • channel
  • DIMM(Dual In-Line Memory Module)
  • rank
  • chip
  • bank
  • cell (row, column)

参考资料:

  1. Predicting DRAM-Caused Node Unavailability in Hyper-Scale Clouds(DSN’22)
  2. 内存结构
  3. 内存基本概念