本文将mark下Intel Advanced Performance Extensions(APX)的相关notes。

Overview

Intel Advanced Performance Extensions (Intel APX) expands the Intel 64 instruction set architecture with access to more registers and adds various new features that improve general-purpose performance. The extensions are designed to provide efficient performance gains across a variety of workloads without significantly increasing silicon area or power consumption of the core.

Intel APX doubles the number of general-purpose registers (GPRs) from 16 to 32. This allows the compiler to keep more values in registers. As a result, code compiled with Intel APX contains 10% fewer loads and more than 20% fewer stores than the same code compiled for an Intel® 64 baseline. Register accesses are not only faster, but they also consume significantly less dynamic power than complex load and store operations.

Changes

  • Doubles the number of general purpose registers from 16 to 32
  • New three operand instructions (e.g. adding ability to subtract register1 from register2, and place the result in register3)
  • New instructions to PUSH/POP two general purpose registers at once

XSAVE-enabled

New Register State

APX register state is managed by the XSAVE instruction set, with its state component number assigned to 19, following XTILEDATA.

XSAVE Buffer Offset

  • In the compacted format used (for the in-kernel buffer), the APX state will appear at a later position in the buffer.
  • In the non-compacted format (used for signal, ptrace, and KVM ABIs), APX is assigned a lower offset, occupying the space previously reserved for the deprecated MPX state.

参考资料:

  1. https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html
  2. Introducing Intel® Advanced Performance Extensions (Intel® APX)
  3. [PATCH RFC v1 00/20] KVM: x86: Support APX feature for guests
  4. [PATCH RFC v1 00/11] x86: Support Intel Advanced Performance Extensions
  5. Intel APX