本文将记录PCI Express Configuration Space相关笔记。

1. Background

The PCI Express bus extends the Configuration Space from 256 bytes to 4096 bytes. This extended configuration space cannot be accessed using the legacy PCI method (through ports 0xCF8 and 0xCFC).

In the beginning there was a configuration space, for each PCI device function, of 256 bytes.
This space was accessed using the PCI legacy mechanism (we can ignore the fact there were two mechanisms) at ports 0xcf8 and 0xcfc.

The PCIe extended this space from 256 bytes to 4KiB and introduced a new mechanism to access the configuration space (all of it).

So, to recap:

  • There is a single PCI configuration space of 4KiB. It is divided into a PCI 3.0 Compatible region (from 0x000 to 0x0ff) and PCIe extended configuration region (from 0x100 to 0xfff).
  • There are two mechanism to access the PCI configuration space. One is the legacy mechanism at 0xcf8/0xcfc the other one is a memory mapped area.
  • The Legacy mechanism can only access the compatibility region (the first 256 bytes).
  • The ECAM can access all of the space.

2. ECAM

Enhanced Configuration Access Mechanism (ECAM)

PCI Express extends the Configuration Space to 4096 bytes per Function as compared to 256 bytes allowed by PCI Local Bus Specification.

PCI Express Configuration Space is divided into a PCI 3.0 compatible region, which consists of the first 256 bytes of a Function’s Configuration Space, and a PCI Express Extended Configuration Space which consists of the remaining Configuration Space .

The PCI 3.0 compatible Configuration Space can be accessed using either the mechanism defined in the PCI Local Bus Specification or the PCI Express Enhanced Configuration Access Mechanism (ECAM).

Accesses made using either access mechanism are equivalent. The PCI Express Extended Configuration Space can only be accessed by using the ECAM.

The base address of the MMIO area for the configuration space of each PCIe devices in a PCI segment group is given in the ACPI table MCFG.

The MCFG table lists, for each PCI segment group, the first and last (inclusive) bus number of the PCI segment group and the base address of the PCI Express enhanced configuration space.

The MCFG table is setup by the BIOS/UEFI based upon the value of the PCIEXBAR (offset 60h) in the Host Bridge PCI configuration space.

3. Verification

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$ lspci -xxx -s 00:0.0
00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers (rev 02)
00: 86 80 04 59 06 00 90 20 02 00 00 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 70 20
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
40: 01 90 d1 fe 00 00 00 00 01 00 d1 fe 00 00 00 00
50: c1 02 00 00 31 80 00 00 47 00 f0 8f 01 00 00 8b
60: 01 00 00 e0 00 00 00 00 01 80 d1 fe 00 00 00 00
70: 00 00 00 fe 01 00 00 00 00 0c 00 fe 7f 00 00 00
80: 11 00 00 00 00 00 00 00 1a 00 00 00 00 00 00 00
90: 01 00 00 fe 01 00 00 00 01 00 f0 6d 02 00 00 00
a0: 01 00 00 00 02 00 00 00 01 00 00 6e 02 00 00 00
b0: 01 00 00 8c 01 00 80 8b 01 00 00 8b 01 00 00 90
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 09 00 10 01 21 60 61 7a dc 80 15 14 00 c0 06 00
f0: 00 00 00 00 c8 0f 09 00 00 00 00 00 00 00 00 00


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$ cat /proc/iomem | grep MMCONFIG
e0000000-efffffff : PCI MMCONFIG 0000 [bus 00-ff]

$ dmesg | grep -i MCFG
[    0.011632] ACPI: MCFG 0x000000008A5D0060 00003C (v01 INTEL  NUC7i5DN 00000043 MSFT 00000097)

$ dmesg | grep -i MMCONFIG
[    0.149772] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
[    0.149772] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820

参考资料:

  1. How to access PCIe configuration space?
  2. How to access pci express configuration space via MMIO?
  3. How to read extended PCIE configuration space in Linux?
  4. 10th gen core families datasheet vol 2 datasheet