本文将mark下FPGA基本概念的相关notes。

Field Programmable Gate Arrays (FPGAs) are “a sea” of logic, arithmetic, and memory elements, which users can configure to implement custom compute circuits. FPGA compute capacity is determined by the area available for the circuits.

FPGA development

FPGAs can be seen as “software defined” hardware. The software definition, a design, is implemented using register transfer languages (RTL) such as Verilog. Additionally, designers can use high-level synthesis (HLS) tools to generate RTL, e.g., from a restricted version of C++. However, HLS C++ programs are different from CPU programs, and must follow certain rules, including explicit exposure of fine-grain pipeline- and task- parallelism to achieve high performance. Implementation tools then compile the design into an FPGA image targeting specific hardware.

Finally, users can load the image onto an FPGA (slow, up to a few seconds), entirely replacing the previous design. Some FPGAs support partial reconfiguration to replace only a subset of the entire FPGA, a much faster process (milliseconds), which unfortunately incurs significant area overheads.

FPGA sharing

There are three ways to share an FPGA: space partitioning, coarse-grain, and fine-grain time sharing.

space partitioning

Space partitioning divides FPGA resources into disjoint sets used by different AFUs(Accelerator Functional Units). If shared I/O interfaces (memory, PCIe bus) are securely isolated and multiplexed, this method enables low-overhead FPGA sharing among mutually distrustful AFUs but requires larger FPGAs to fit them all.

Coarse-grain time sharing

Coarse-grain time sharing dynamically switches AFUs via full or partial reconfiguration. It incurs high switching latency.

Fine-grain time sharing

Fine-grain time sharing allows multiple CPU applications to use the same AFU. The AFU implements the context switch internally, in hardware. Packet processing applications such as AccelNet use this approach to process each packet in the context of its associated flow. Such AFUs oversee switching between the contexts(此类AFU负责管理不同上下文之间的切换); therefore this type of sharing requires AFUs to be trusted to ensure fair use and state isolation between their users.


参考资料:

  1. NICA: An Infrastructure for Inline Acceleration of Network Applications