Notes about Intel TLB Topology

本文将mark下Intel TLB Topology的相关notes。

Architecture

Overview

L1 TLBs

Modern processors implement a group of split L1 TLBs for instructions and data, separated by page size.

• Separate I and D TLBs
• Separate L1 TLBs for Different Page Sizes

L2 TLBs

• Multiple page size support
• Inclusive, mostly-inclusive, or exclusive designs

SDM

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参考资料:

1. TLB;DR: Enhancing TLB-based Attacks with TLB Desynchronized Reverse Engineering
2. Meltdown: Reading Kernel Memory from User Space
3. Appendix L: Advanced Concepts on Address Translation