Some notes about APICv MSR-Based APIC Accesses

MSR-Based APIC Accesses

1. Secondary Processor-Based VM-Execution Controls.Virtualize x2APIC Mode[bit 4] = 1时，VMCS中x2APIC MSR Bitmap的设置依然有效。

2. WRMSR ICR, no APIC Write VM Exit, has potential security issues?
   Solution: set VMCS MSR Bitmap to trap ICR register write.